The U.S. microelectronics industry, valued at over $300 billion in 1995, is confronted with technological changes at an unprecedented pace and urgency. This is due partially to increased consumer expectations, rapid product evolutions, and heightened international competition. In response to these pressures, the U.S. semiconductor and module interconnection industries, representing combined sales of over $54 billion in 1995, have taken the landmark steps of developing technology roadmaps. These two roadmaps, entitled The National Technology Roadmap for Semiconductors and The National Technology Roadmap for Electronic Interconnects, produced by the Semiconductor Industry Association and the Institute for Interconnecting and Packaging Electronic Circuits, respectively, identify roadblocks and performance characteristics for the manufacture of globally competitive products. Significant portions of these roadmaps address the packaging and interconnection of semiconductor devices, a technology which now amounts to over one-third the delivered cost of integrated circuits.

To assist this strategic and rapidly growing U.S. industry, the NIST Materials Science and Engineering Laboratory has embarked on a new program in electronics packaging and interconnection that addresses industry's most pressing challenges surrounding the utilization of advanced materials and material processes. With a specific mission to develop and deliver to U.S. electronics and electronic materials industries, measurement tools and data for materials and processes used in semiconductor packaging, module interconnection and component assembly, the strategy used to implement this program is based upon three primary needs.

• Develop techniques and procedures for making in-situ, in-process and in-use measurements on materials and material assemblies having micrometer- and submicrometer-scale dimensions.

• Record and quantify the divergence of material properties from their bulk values as dimensions are reduced and interfaces are approached.

• Develop fundamental understanding of materials needed for future packaging, interconnection and assembly schemes.

This strategy is the outgrowth of two industry-led workshops conducted at NIST. The first, conducted in 1990, set the course for the Laboratory's emerging plans in packaging, interconnection and assembly. The second, conducted in early 1994, identified a series of cross-cutting barriers, critical technical challenges and opportunities for NIST in materials science and engineering deemed most needed by the U.S. microelectronics industry. The results of this workshop are contained in NISTIR 5520, Metrology and Data for Microelectronics Packaging and Interconnection.

Now in its second full year of funding, the program has in place a portfolio of projects involving the talents and operations of metallurgists, polymer scientists, and materials reliability specialists. During this period, the MSEL program has developed numerous single- company and consortia-based collaborations that involve over twenty-three U.S. companies; fifteen universities; four other government agencies or laboratories; and eight consortia, standards bodies and associations. These collaborations have resulted in forty-six technical publications, sixteen of which were published in 1995, and numerous individual accomplishments that directly impact industry's research and development needs.

Projects

Alternatives to Lead-based Solders
Electrochemical Characterization of Solders
Solderability Measurements and Optimization
Solder Jet Printing for Microelectronics Applications
Solder Interconnect Engineering
Stress Measurement in Electronic Packaging

For further information on any aspect of the Electronic Packaging and Interconnection Program, please contact Michael A. Schen @ 301-975-6741 or e-mail requests to michael.schen@nist.gov.

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Last modified: Mon Jan 06 09:46:15 1997 Metallurgy Webmeister